Model of Switched-Capacitor Programmable Voltage Reference: Optimization for Ultra Low-Power Applications

This paper proposes an analytical model for the optimized design of a switched-capacitor programmable voltage reference (SC-PVREF). This PVREF topology guarantees a straightforward design, easy portability across different technology nodes, and does not require any special technology option. The developed model allows the study of the trade-offs and the a priori evaluation of the system performance. Circuit optimization is carried out with MATLAB and permits SC-PVREF to achieve current consumptions of tens of nanoampere, suitable for ultra low-power applications

The Digital Kernel Perceptron

In this paper, we show that a kernel-based perceptron can be efficiently implemented in digital hardware using very few components. Despite its simplicity, the experimental results on standard data sets show remarkable performance in terms of generalization error

Multi-function ESD protection circuit for UHF RFID devices in CMOS technology

The design and implementation of an electrostatic discharge protection suitable for UHF RFID devices in CMOS technology is presented. The circuit implements three fundamental functions for the RF interface: power limiting, backscatter modulation and electrostatic discharge protection. Since all functions are achieved by the same MOS device the additional shunt capacitance at the RF inputs is limited. Therefore the maximum reading distance of the RFID device is improved without sacrificing the electrostatic protection level

Power Management Circuits for Low-Power RF Energy Harvesters

The paper describes the design and implementation of power management circuits for RF energy harvesters suitable for integration in wireless sensor nodes. In particular, we report the power management circuits used to provide the voltage supply of an integrated temperature sensor with analog-to-digital converter. A DC-DC boost converter is used to transfer efficiently the energy harvested from a generic radio-frequency rectifier into a charge reservoir, whereas a linear regulator scales the voltage supply to a suitable value for a sensing and conversion circuit. Implemented in a 65 nm CMOS technology, the power management system achieves a measured overall efficiency of 20%, with an available power of 4.5 μW at the DC-DC converter input. The system can sustain a temperature measurement rate of one sample/s with an RF input power of −28 dBm, making it compatible with the power levels available in generic outdoor environments

Memory Devices and A/D Interfaces: Design Trade-offs in Mixed-Signal Accelerators for Machine Learning Applications

This tutorial focuses on memory elements and analog/digital (A/D) interfaces used in mixed-signal accelerators for deep neural networks (DNNs) in machine learning (ML) applications. These very dedicated systems exploit analog in-memory computation (AiMC) of weights and input activations to accelerate the DNN algorithm. The co-optimization of the memory cell storing the weights with the peripheral circuits is mandatory for improving the performance metrics of the accelerator. In this tutorial, four memory devices for AiMC are reported and analyzed with their computation scheme, including the digital-to-analog converter (DAC). Moreover, we review analog-to-digital converters (ADCs) for the quantization of the AiMC results, focusing on the design trade-offs of the different topologies given by the context

"Next Generation EU" Cities

As the world enters a new year, the Covid-19 pandemic is still upsetting our daily lives. And as 75% of EU citizens live in urban areas, cities are the most prominent stage both for responding to the health crisis, and for seizing opportunities to recover and move forward. Meanwhile, in 2020, EU countries agreed to Next Generation EU, a €750 billion recovery package that represents a once-in-a-generation opportunity. This report argues that cities should be given more say over how post-pandemic national recovery plans pan out between here and 2026, when all projects are supposed to be wrapping up. Indeed, the success of the EU recovery plans will hinge upon what cities do, or they don’t do over the next five years. How are cities rethinking their role within the “twin” green and digital transitions? How can they achieve gender parity, reduce inequalities, and preserve a vibrant cultural life?Publishe

Inner nuclear membrane protein targeting studied by quantitative live cell imaging and RNAi screening

During interphase of cycling cells, the surface of the nuclear envelope (NE), consisting of inner and outer nuclear membrane (I/ONM) fused at each nuclear pore complex (NPC) approximately doubles. This organelle growth requires homeostatic synthesis and delivery of lipids and proteins to maintain a fully functional NE and prepare for the next nuclear division. INM proteins reside specifically in the INM and carry out several essential functions. They constitute a heterogeneous class of transmembrane proteins and are delivered by the probably least understood cellular membrane trafficking pathway. How targeting of the different classes of INM proteins is achieved and how many trafficking and regulatory mechanisms exist is currently not well understood. One reason is that unlike for other trafficking pathways such as membrane secretion, it has so far been impossible to visualize INMP trafficking in live cells. To address this point in the first part of my project I have developed a novel INMP trafficking reporter system (named Target-INM) that allows the acute release of INM proteins from the ER to the INM. The system is based on trapping INM proteins in the ER with a cleavable retention domain that can be removed by acute activation of a protease. I applied this generic reporter strategy to a set of INM proteins (LBR, Lap2beta, Tor1AIP1, Man1 and Sun1) that represent the major transmembrane protein classes and could image and quantify their synchronous delivery from the ER to the INM in interphase with high spatial and temporal resolution. Exploiting this assay, I screened by siRNA knockdown and automated high resolution confocal time-lapse microscopy 96 candidate genes for their requirement in LBR targeting. These genes include nucleoporins, importins, lamins as well as NE and ER membrane proteins. I identified several genes that affect LBR INM targeting. Together with Antonio Politi, a postdoc in the lab, I developed a mathematical model of the INM protein targeting process that I used to fit the kinetic signatures of the different transport phenotypes and cluster the scoring genes into three major phenotypic classes providing evidences for the basic principle governing INM protein targeting. Comparing the genetic requirements for targeting of the different INMP protein classes should now put us in a position to define the number of molecularly distinct trafficking pathways from the ER to the INM

CMOS Interface Circuits for High-Voltage Automotive Signals

Abstract: The acquisition of high-voltage signals from sensors and actuators in an internal-combustion engine is often required for diagnostic purposes or in the case of conversion to alternative fuels, such as hydrogen, natural gas, or biogas. The integration of electronic interfaces and acquisition circuits in a single device provides benefits in terms of component-count reduction and performance. Nonetheless, the high voltage level of the involved signals makes on-chip design challenging. Addi- tionally, the circuits should be compatible with the CMOS technology, with limited use of high-voltage options and a minimum number of off-chip components. This paper describes the design and the implementation in 350 nm CMOS technology of electronic interfaces and acquisition circuits for typical high-voltage signals of automotive context. In particular, a novel co-design of dedicated voltage clamps with electro-static discharge (ESD) protections is described. The proposed circuits require only a single off-chip resistor, and they are suitable for the acquisition of signals with peak voltages up to 400 V. The measured performance of the silicon prototypes, in the [−40 °C, +125 °C] temperature range, make the proposed electronic interfaces suitable for the automotive domain

An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems

This paper proposes a novel architecture for the generation of a programmable voltage reference: the background- calibrated (BC)-PVR. Our mixed-signal architecture periodically calibrates a static ultra low-power voltage reference generator, from an accurate bandgap reference. The portion of the chip used for the calibration can be powered down with a programmable duty-cycle. The system aims to fully exploit the small temperature derivative vs time DT of several application domains to minimize the average current consumption. The BC-PVR has been designed and implemented in TSMC 55-nm CMOS technology, and it achieves the largest reported programming reference output ◦range [0.42 - 2.52] V, over the temperature range [-20 , 85] C. The duty-cycle mode allows nanoampere current consumption, and the large design flexibility permits to optimize the system performance for the specific application. These features make the BC-PVR very well-suited for power-constrained electronic systems